數(shù)字VLSI芯片設(shè)計(jì)

內(nèi)容概要

本書介紹如何使用Cadence和Synopsys公司的CAD工具來(lái)實(shí)際設(shè)計(jì)數(shù)字VLSI芯片。讀者通過(guò)本書可以循序漸進(jìn)地學(xué)習(xí)這些CAD工具，并使用這些軟件設(shè)計(jì)出可制造的數(shù)字集成電路芯片。本書內(nèi)容按集成電路的設(shè)計(jì)流程編排，包括CAD設(shè)計(jì)平臺(tái)、電路圖輸入、Verilog仿真、版圖編輯、標(biāo)準(zhǔn)單元設(shè)計(jì)、模擬和數(shù)?；旌闲盘?hào)仿真、單元表征和建庫(kù)、Verilog綜合、抽象形式生成、布局布線及芯片總成等工具；每一工具的使用都以實(shí)例說(shuō)明，最后給出了一個(gè)設(shè)計(jì)簡(jiǎn)化MIPS微處理器的完整例子。本書可與有關(guān)集成電路設(shè)計(jì)理論的教科書配套使用，可作為高等院校有關(guān)集成電路設(shè)計(jì)理論類課程的配套教材和集成電路設(shè)計(jì)實(shí)踐類課程的教科書，也可作為集成電路設(shè)計(jì)人員的培訓(xùn)教材和使用手冊(cè)。

作者簡(jiǎn)介

作者：(美國(guó))布魯范德

書籍目錄

1　Introduction　1.1  CAD Tool Flows    1.1.1  Custom VLSI and Cell Design Flow    1.1.2  Hierarchical Cell/Block ASIC Flow  1.2  What This Book Is and Isn't  1.3  Bugs in the Tools?  1.4  Tool Setup and Execution Scripts   1.5  Typographical Conventions2　Cadence DFII and ICFB　2.1  Cadence Design Framework　2.2  Starting Cadence　2.3  Summary3　Composer Schematic Capture　3.1  Starting Cadence and Making a New  　Working Library　3.2  Creating a New Cell    3.2.1  Creating the Schematic View of a Full Adder    3.2.2  Creating the Symbol View of a Full Adder    3.2.3  Creating a Two-Bit Adder Using the FullAdder Bit　3.3  Schematics that Use Transistors　3.4  Printing Schematics    3.4.1  Modifying PostScript Plot Files  3.5  Variable, Pin, and Cell Naming Restrictions  3.6  Summary4  Verilog Simulation  4.1  Verflog Simulation of Composer Schematics  　4.1.1  Verilog-XL: Simulating a Schematic    4.1.2  NC_Verilog: Simulating a Schematic  4.2  Behavioral Verilog Code in Composer    4.2.1  Generating a Behavioral View    4.2.2  Simulating a Behavioral View  4.3  Stand-Alone Verilog Simulation    4.3.1   Verilog-XL    4.3.2  NC_Verilog    4.3.3  VCS  4.4  Timing in Verilog Simulations     4.4l  Behavioral Versus Transistor Switch Simulation    4.4.2  Behavioral Gate Timing    4.4.3  Standard Delay Format (SDF) Timing    4.4.4  Transistor Timing　4.5  Summary5　Virtuoso Layout Editor  5.1  An Inverter Schematic  　5.1.1  Starting Cadence kfb    5.1.2  Making an Inverter Schematic    5.1.3  Making an Inverter Symbol  5.2  Layout for an Inverter    5.2.1  Creating a New layout View    5.2.2  Drawing an nmosTransistor    5.2.3  Drawing a pmos Transistor    5.2.4  Assembling the Inverter from the Transistor Layouts    5.2.5  Using Hierarchy in Layout    5.2.6  Virtuoso Command Overview　……6  Standard Cell Design Template7  Spectre Analog Simulator8  Cell Characterization9  Verilog Synthesis10  Abstract Generation11  SOC Encounter Place and Route12  Chip Assembly13  Design ExampleA  Tool and Setup ScriptsB  Scripts to Drive the ToolsC  Technology and Cell LibrariesBibliographyIndex

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