專用集成電路時程序驗證

前言

　　微電子技術(shù)是信息科學(xué)技術(shù)的核心技術(shù)之一，微電子產(chǎn)業(yè)是當代高新技術(shù)產(chǎn)業(yè)群的核心和維護國家主權(quán)、保障國家安全的戰(zhàn)略性產(chǎn)業(yè)。我國在《信息產(chǎn)業(yè)“十五”計劃綱要》中明確提出：堅持自主發(fā)展，增強創(chuàng)新能力和核心競爭力，掌握以集成電路和軟件技術(shù)為重點的信息產(chǎn)業(yè)的核心技術(shù)，提高具有自主知識產(chǎn)權(quán)產(chǎn)品的比重。發(fā)展集成電路技術(shù)的關(guān)鍵之一是培養(yǎng)具有國際競爭力的專業(yè)人才?！　∥㈦娮蛹夹g(shù)發(fā)展迅速，內(nèi)容更新快，而我國微電子專業(yè)圖書數(shù)量少，且內(nèi)容和體系不能反映科技發(fā)展的水平，不能滿足培養(yǎng)人才的需求，為此，我們系統(tǒng)挑選了一批國外經(jīng)典教材和前沿著作，組織分批出版。圖書選擇的幾個基本原則是：在本領(lǐng)域內(nèi)廣泛采用，有很大影響力；內(nèi)容反映科技的最新發(fā)展，所述內(nèi)容是本領(lǐng)域的研究熱點；編寫和體系與國內(nèi)現(xiàn)有圖書差別較大，能對我國微電子教育改革有所啟示。本套叢書還側(cè)重于微電子技術(shù)的實用性，選取了一批集成電路設(shè)計方面的工程技術(shù)用書，使讀者能方便地應(yīng)用于實踐?！　∥覀冋嬲\地希望，這套叢書能對國內(nèi)高校師生、工程技術(shù)人員以及科研人員的學(xué)習(xí)和工作有所幫助，對推動我國集成電路的發(fā)展有所促進。也衷心期望著廣大讀者對我們一如既往的關(guān)懷和支持，鼓勵我們出版更多、更好的圖書。

內(nèi)容概要

　　《專用集成電路時序驗證》是近10年來惟一一本專門討論時序及時序驗證的專著，共分4章。《專用集成電路時序驗證》全面討論了靜態(tài)時序驗證的各方面內(nèi)容；全書不僅緊密結(jié)合電路圖和波形圖進行講解，還結(jié)合Synopsys公司的邏輯綜合和靜態(tài)時序分析工具講解如何通過命令加以實現(xiàn)；介紹過程中不僅從理論上闡述了延遲模型，而且注重實踐環(huán)節(jié)，引入了大量實際示例加以深入探討。這種寫作風(fēng)格將促進讀者能夠更全面、細致地理解所講內(nèi)容，因此《專用集成電路時序驗證》十分適合自學(xué)。

作者簡介

　　內(nèi)庫加（Farzad Nekoogar） is Director of Design Services at SiliconDesigns International. Farzad has extensive practical expe-rience verifying timing ofASICs， FPGAs， and systems-on-a-chip. He is the author of Digital Control Using Digital Sig-nal Processing， published by Prentice Hall PTR. He has lec-tured at the University of California at Berkeley on signalprocessing， control systems， and theoretical physics （specifi-cally， Superstring Theory）. He is currently a lecturer at theDepartment of Applied Science at the University of Califor-nia at Davis.　　Farzad， seen here in December 1992 at Stanford University， with Sir Roger Penrose.Farzad writes： "In this book we try to solve timing issues related to design of micro-chips. I am honored to be pictured here with Sir Roger Penrose， one of the most bril-liant scientists of all time， who has authored some of the most complex theories aboutspace-time， contributing a lot to our understanding of the universe."

書籍目錄

List of FiguresList of TablesPrefaceAcknowledgments1 Introduction to Timing Verification1.1 Introduction1.2 Overview of Timing Verification1.2.1 Intrinsic vs. Extrinsic Delay1.2.2 Path Delay1.3 Interface Timing Analysis2 Elements of Timing Verification2.1 Introduction2.2 Clock Definitions2.2.1 Gated Clocks2.2.2 Clock Skews and Multiple Clock Groups2.2.3 Multifrequency Clocks2.2.4 Multiphase Clocks2.3 More on STA2.3.1 False Paths2.3.2 Multicycle Path Analysis2.3.3 Timing Specifications2.3.4 Timing Checks2.4 Timing Analysis of Phase-Locked Loops2.4.1 PLL Basics2.4.2 PLL Ideal Behavior2.4.3 PLL Errors3 Timing in ASICs3.1 Introduction3.2 Prelayout Timing3.2.1 RTL vs. Gate-Level Timing3.2.2 Timing in RTL Code3.2.3 Delay with a Continuous Assignment Statement3.2.4 Delay in a Process Statement3.2.6 Intra-Assignment Delays3.2.6 The Verilog Specify Block3.2.7 Timing in-Gate Level Code3.2.8 Synthesis and Timing Constraints3.2.9 Design Rule Constraints3.2.10 Optimization ConstrAints3.2.11 Gate and Wire-Load Models3.2.12 The Synthesis Flow3.2.13 Synthesis Tips3.2.14 Back Annotation to Gate-Level RTL3.3 Post. layout Timing3.3.1 Man-A1 Line-Propagation Delay Calculations3.3.2 Signal-Line Capacitance Calculation3.3.3 Signal Line Resistance Calculation3.3.4 Signal Trace RC Delay Evaluation3.4 ASIC Sign-Off Checklist3.4.1 Library Development3.4.2 Functional Specification3.4.3 RTL Coding3.4.4 Simulations of RTL3.4.5 Logic Synthesis3.4.6 Test Insertion and ATPG3.4.7 Postsynthesis Gate-Level Simulation or Static Timing Analysis3.4.8 Floorplsnning3.4.9 Place and Route3.4.10 Final Verification of the Extracted Netlist3.4.11 Mask Generation and Fabrication3.4.12 Testing4 ProgrAmmable Logic Based Design4.1 Introduction4.2 Programmable Logic Structures4.2.1 Logic Block4.2.2 Input/Output Block4.2.3 Routing Facilities4.3 Design Flow4.4 Timing Parameters4.4.1 Timing Derating Factors4.4.2 Grading Programmable Logic Devices by Speed4.4.3 Beet-Case Delay Values4.5 Timing Analysis4.5.1 Actel ACT FPGA Fsmily4.5.2 Actel ACT 3 Architecture4.5.3 Actel ACT 3 Timing Model4.5.4 Altera FLEX 80004.5.5 Altera FLEX 8000 Architecture4.5.6 Altera FLEX 8000 Timing Model4.5.7 Xilinx XC3000/XC4000 FPGA Families4.5.8 Xilinx XC9500 CPLD4.5.9 Xilinx XC9500 CPLD Architecture4.5.10 Xilinx XC9500 CPLD Timing Model4.6 HDL Synthesis4.7 Software Development Systems4.7.1 Timing Constraints4.7.2 Operating Conditions4.7.3 Static Timing Analysis4.7.4 Vendor-Specific Timing-Verification Tools4.7.5 Actel Designer4.7.6 Altera MAX+PLUS II4.7.7 Xilinx XACT/M1A PrimeTimeB PearlC TimingDesignerD Transistor-Level Timing VerificationReferencesIndexAbout the Author

章節(jié)摘錄

　　Table 1.3 reveals how the input signals determine which paththrough the circuit drives the output. Whenever the input signal e is ne, the values of the other input signals are irrelevant because theone on input e forces the output of the NOR gate to zero. Essentiallythe same situation occurs on line 2 of Table 1.3. The value on input ddetermines the output value. Line 3 shows the conditions where theoutput depends on input a. Line 4 is a more interesting case becausethe path to the output depends on the order of input signal transi-tions. If the input signals are 00000 then become 10000, the transi-tion goes through path cl-c2-c4-c5-c6. The transition 11000 to 10000takes the c2-c4-c5-c6 path while the 10100 to 10000 transition goesthrough the c3-c4-c5-c6 path. In this circuit, the delays from b-outand c-out are the same, but gate and interconnect delays could bedifferent and change the result. The inputs of lines 5 and 6 activatelogic that forces the paths c-out and b-out respectively to determinethe output value. The slowest path between b-out and c-out deter-mines the delay in line 7 only if the transition is from 10000 to11100. The delay path is already set and possibly settled with transi-tions from 10100 to 11100 （c-out） and 11000 to 11100 （b-out）.　　As a result of understanding the circuits response to inputstimuli, the timing analyzer knows that every path is capable ofproducing a response at the output, so it must consider all pathswhen determining delay. In this specific case, the longest path isfrom a-out through c 1-c2-c4-c5-c6 and it is traversed during two dif-ferent transitions: lines 3 and 4.　　In chapter 2 we will consider false paths. False paths are logicpaths that are not synthesized because they are functionallyblocked. These paths are recognized by static timing analyzers asunconstrained paths. One example of false paths is the clocks thatare not harmonically related to each other.

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