Verilog HDL高級數(shù)字設計

前言

　　Simplify,Clarify, and Verify　　Behavioral modeling with a hardware description language （HDL） is the key to modern design of application-specific integrated circuits （ASICs）. Today, most designers use an HDL-based design method to create a high-level, language-based, abstract description of a circuit, and verify its functionality and timing. The language used to teach design methodology in the first edition of this text, IEEE 1464-1995, has undergone two revisions to improve the effectiveness and efficiency of the language: IEEE 1364-2001 followed by a revision in 2005, known as Verilog-2001 and Verilog-2005, respectively.　　The motivation behind this edition is basically the same as that which guided the first edition: students preparing to contribute to a productive design team must know how to use a HDL at key stages of the design flow. Thus, there is a need for a course going beyond the basic principles and methods learned in a first course in digital design. This book is written for such a course.　　The quantity of books discussing HDLs far exceeds that which was available at the time of the first edition, and most of these are still oriented toward explanations of language syntax, rather than toward design, and are not well-suited for classroom use. Our focus is on design methodology enabled by an HDL. Thus, the language itself has a subordinate role. In this edition, we have made a strong effort to demonstrate by examples the importance of partitioning a digital machine to expose its datapath, status （feedback） signals, and controller （finite state machine）.This effort leads, we think, to a much clearer and straightforward approach to designing and verifying complex digital machines. We present an abundance of simulation results, with annotation to help students （1） understand the operation of a sequential machine and （2） appreciate the time-sequential interaction between the signals produced by the controller, the operations in the datapath, and the signals reported back to the controller from the datapath, all with the aim of developing synthesizable, latch-free, race-free designs.

內(nèi)容概要

本書依據(jù)數(shù)字集成電路系統(tǒng)工程開發(fā)的要求與特點，利用Verilog HDL對數(shù)字系統(tǒng)進行建模、設計與驗證，對ASIC/FPGA系統(tǒng)芯片工程設計開發(fā)的關鍵技術與流程進行了深入講解，內(nèi)容包括：集成電路芯片系統(tǒng)的建模、電路結構權衡、流水、多核微處理器、功能驗證、時序分析、測試平臺、故障模擬、可測性設計、邏輯綜合、后綜合驗證等集成電路系統(tǒng)的前后端工程設計與實現(xiàn)中的關鍵技術及設計案例。書中以大量設計實例敘述了集成電路系統(tǒng)工程開發(fā)需遵循的原則、基本方法、實用技術、設計經(jīng)驗與技巧。    本書既可作為電子與通信、電子科學與技術、自動控制、計算機等專業(yè)領域的高年級本科生和研究生的教材或參考資格，也可用于電子系統(tǒng)設計及數(shù)字集成電路設計工程師的專業(yè)技術培訓。

作者簡介

Michael D.Ciletti，科羅拉多大學電氣與計算機工程系教授。研究方向包括通過硬件描述語言進行數(shù)字系統(tǒng)的建模、綜合與驗證、系統(tǒng)級設計語言和FPGA嵌入式系統(tǒng)。其著作還有Digital Design，F(xiàn)ourth Edition(其翻譯版和影印版均由電子工業(yè)出版社出版)。作者曾在惠普、福特微電子和

書籍目錄

1 Introduction to Digital Design Methodology   1.1 Design Methodology—An Introduction   1.2 IC Technology Options   1.3 Overview   References 2 Review of Combinational Logic Design   2.1 Combinational Logic and Boolean Algebra   2.2 Theorems for Boolean Algebraic Minimization   2.3 Representation of Combinational Logic   2.4 Simplification of Boolean Expressions   2.5 Glitches and Hazards   2.6 Building Blocks for Logic Design   References   Problems 3 Fundamentals of Sequential Logic Design   3.1 Storage Elements   3.2 Flip-Flops   3.3 Busses and Three-State Devices   3.4 Design of Sequential Machines   3.5 State-Transition Graphs   3.6 Design Example: BCD to Excess-3 Code Converter   3.7 Serial-Line Code Converter for Data Transmission   3.8 State Reduction and Equivalent States   References   Problems 4 Introduction to Logic Design with Verilog   4.1 Structural Models of Combinational Logic   4.2 Logic System, Design Verification, and Test Methodology   4.3 Propagation Delay   4.4 Truth Table Models of Combinational and Sequential Logic with Verilog   References   Problems 5 Logic Design with Behavioral Models of Combinational and Sequential Logic   5.1 Behavioral Modeling   5.2 A Brief Look at Data Types for Behavioral Modeling   5.3 Boolean Equation-Based Behavioral Models of Combinational Logic   5.4 Propagation Delay and Continuous Assignments   5.5 Latches and Level-Sensitive Circuits in Verilog   5.6 Cyclic Behavioral Models of Flip-Flops and Latches   5.7 Cyclic Behavior and Edge Detection   5.8 A Comparison of Styles for Behavioral Modeling   5.9 Behavioral Models of Multiplexers, Encoders, and Decoders   5.10 Dataflow Models of a Linear-Feedback Shift Register   5.11 Modeling Digital Machines with Repetitive Algorithms   5.12 Machines with Multicycle Operations   5.13 Design Documentation with Functions and Tasks: Legacy or Lunacy?   5.14 Algorithmic State Machine Charts for Behavioral Modeling   5.15 ASMD Charts   5.16 Behavioral Models of Counters, Shift Registers, and Register Files   5.17 Switch Debounce, Metastability, and Synchronizers for Asynchronous Signals   5.18 Design Example: Keypad Scanner and Encoder   References   Problems 6 Synthesis of Combinational and Sequential Logic 7 Design and Synthesis of Datapath Controllers 8 Programmable Logic and Storage Devices 9 Algorithms and Architectures for Digital Processors 10 Architectures for Arithmetic Processors 11 Postsynthesis Design Tasks A Verilog Primitives B Verilog Keywords C Verilog Data Types D Verilog Operators E Verilog Language Formal Syntax F Verilog Language Formal Syntax G Additional Features of Verilog H Flip-Flop and Latch Types I Verilog-2001, 2005 J Programming Language Interface K Web sites L Web-Based Resources Index

章節(jié)摘錄

　　HDL-based designs are easier to debug than schematics.A behavioral descrip-tion encapsulating complex functionality hides underlying gate-level detail，so there isless information to cope with in trying to isolate problems in the functionality of thedesign.Furthermore.if the behavioral description is functionally correct.it is a goldstandard for subsequent gate.1evel realizations.　　HDL-based designs incorporate documentation within the design by using de-scriptive names，by including comments to clarify intent，and by explicitly specifying ar-chitectural relationships.thereby reducing the volume of documentation that must bekept in other archives.Simulation of a language.based model explicitly specifies thefunctionality of the design.Since the language is a standard.documentation of a designcan be decoupled from a particular vendors tools.　　Behavioral modeling is the predominant descriptive style used by industry，en-abling the design of massive chips.Behavioral modeling describes the functionality Dr adesign by specifying what the designed circuit will do.not how to build it in hardware.It specifies the input-output model of a logic circuit and suppresses details about phys-ical，gate-level implementation.　　Behavioral modeling encourages designers to（1）rapidly create a behavioral pro-totype of a design（without binding it to hardware details），（2）verify its functionality,and then （3） use a synthesis tool to optimize and map the design into a selected physi-cal technology.If the model has been written in a synthesis-ready style，the synthesistool will remove redundant logic.perform tradeoffs between alternative architecturesand／or multilevel equivalent circuits.and ultimately achieve a design that is compatiblewith area or timing constraints.By focusing the designers attention on the functional-ity that is to be implemented rather than on individual logic gates and their intercon-nections.behavioral modeling provides the freedom to explore alternatives to a designbefore committing it to production.　　Aside from its importance in synthesis.behavioral modeling provides flexibilityto a design project by allowing parts of the design to be modeled at difierent levels of abstraction.The Verilog language accommodates mixed levels of abstraction so thatportions of the design that are implemented at the gate level（i-e structurally）can beintegrated and simulated concurrently with other parts of the design that are repre-sented by behavioral descriptions.　　1.1.4 Simulation and Functional VerificationThe functionality of a design is verified（Step 4 in Figure 1-1） either by simulation or byformaI methods［7］.Our discussion will focus on simulation that is reasonable for the size of circuits we can present here.The design flow iterates back to Step 3 untiI thefunctionality of the design has been verified.The verification process is threefold；itincludes（1）development of a test plan，（2）development of a testbench，and（3）execu-tion of the test.

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