Verilong數(shù)字系統(tǒng)設(shè)計(jì)

內(nèi)容概要

　　本書主要講述基于IEEE Std 1364-2001版本的Verilog硬件描述語(yǔ)言，著重講述了使用Verilog進(jìn)行數(shù)字系統(tǒng)的設(shè)計(jì)、驗(yàn)證及綜合。根據(jù)數(shù)字集成電路設(shè)計(jì)的工程需求，本書重點(diǎn)關(guān)注了testbench的設(shè)計(jì)編寫、驗(yàn)證和測(cè)試技術(shù)，深入講述了基于Verilog HDL的開關(guān)級(jí)、門級(jí)、RTL級(jí)、行為級(jí)和系統(tǒng)級(jí)建模技術(shù)，從而使讀者能盡快掌握硬件電路和系統(tǒng)的高效Verilog編程技術(shù)。書中把RTL描述、電路綜合和testbench驗(yàn)證測(cè)試技術(shù)緊密結(jié)合，給出了多個(gè)從設(shè)計(jì)描述到驗(yàn)證的RTL數(shù)字電路模塊和系統(tǒng)的設(shè)計(jì)實(shí)例。改編者在對(duì)標(biāo)題、重點(diǎn)句子和段落進(jìn)行注解時(shí)，在翻譯的基礎(chǔ)上針對(duì)較難理解的內(nèi)容做了詳細(xì)說(shuō)明。    本書的設(shè)計(jì)與講解由淺入深，既適合高年級(jí)本科生作為雙語(yǔ)教學(xué)教材，也適合作為研究生第一年的雙語(yǔ)課程教材。作為本科生和研究生數(shù)字系統(tǒng)設(shè)計(jì)和計(jì)算機(jī)組織結(jié)構(gòu)的補(bǔ)充，本書也很價(jià)值。

書籍目錄

Chapter 1　Digital System Design Automation with Verilog　1.1　Digital Design Flow　1.2　Verilog HDL 　1.3　Summary　Problems　Suggested ReadingChapter 2　Register Transfer Level Design with Verilog　2.1　RT Level Design　2.2　Elements of Verilog　2.3　Component Description in Verilog　2.4　Testbenches　2.5　Summary 　Problems　Suggested ReadingChapter 3　Verilog Language Concepts　3.1　Characterizing Hardware Languages　3.2　Module Basics　3.3　Verilog Simulation Model　3.4　Compiler Directives　3.5　System Tasks and Functions　3.6　Summary　Problems　Suggested ReadingChapter 4　Combinational Circuit Description　4.1　Module Wires　4.2　Gate Level Logic　4.3　Hierarchical Structures　4.4　Describing Expressions with Assign Statements　4.5　Behavioral Combinational Descriptions　4.6　Combinational Synthesis　4.7　Summary　Problems　Suggested ReadingChapter 5　Sequetial Circuit Description　5.1　Sequential Models　5.2　Basic Memory Components　5.3　Functional Registers　5.4　State Machine Coding　5.5　Sequential Synthesis　5.6　Summary　Problems　Suggested ReadingChapter 6　Component Test Verification　6.1　Testbench　6.2　Testbench Techniques　6.3　Design Verification　6.4　Assertion Verification　6.5　Text Based Testbenches　6.6　Summary　Problems　Suggested ReadingChapter 7　Detailed Modeling　7.1　Switch Level Modeling　7.2　Strength Modeling　7.3　Summary　Problems　Suggested ReadingChapter 8　RT Level Design and Test　8.1　Sequential Multiplier　8.2　von Neumann Computer Model　8.3　CPU Design and Test　8.4　Summary　Problems　Suggested Reading Appendix A　List of KeywordsAppendix B　Frequently Used Syetem Taske and FunctionsAppendix C　Compiler DirectivesAppendix D　Verilog Formal Syntax DefinitionAppendix E　Verilog Assertion Monitors

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