Lattice FPGA/CPLD設(shè)計(jì)

前言

Both CPLDs (complex programmable logic device) and FPGAs (field programmable gate array) were invented approximately 25 years ago.  However, it is only within the past decade that these versatile, reprogrammable logic ICs have become a force to be reckoned with in system design. Where once programmable devices were used primarily for glue logic applications or in the development of prototype designs, today's CPLDs, and particularly FPGAs, have evolved into high-performance low-power chips with advanced IO, memory, DSP blocks, SERDES transceivers and processing resources that make them viable choices for volume production in infrastructure markets such as wireline and wireless.At the same time that programmable logic devices have become less expensive and more capable, ASICs (application-specific integrated circuits) have become prohibitively expensive, and ASSPs (application-specific standard products) too inflexible for product life cycles that often are measured in months.  As a result, the use of programmable logic is expanding to applications and within markets (such as consumer) where previously they were not realistic design choices. This is certainly true of the programmable logic devices offered by Lattice Semiconductor, including their PLDs, FPGAs and programmable Power Management and Clock Management mixed signal devices.The ispMACH 4000ZE CPLDs, for example, are being used in portable, handheld device design applications due to their low power consumption and small size.The Lattice MachXO PLD devices are versatile, "all in one" PLDs that are easy and convenient to design with. Lattice's mid-range ECP3 FPGA families are setting new standards for low powerand high value in wireless, wireline, display and security and surveillance applications. Complementing Lattice's silicon devices is an extensive ecosystem of design tools, reference designs, IP cores, development kits and evaluation boards.

內(nèi)容概要

本書是由lattice公司技術(shù)專家編寫、審校而成的國內(nèi)第一本系統(tǒng)介紹lattice器件及工具軟件的書籍，彌補(bǔ)了目前國內(nèi)沒有權(quán)威的中文lattice器件和工具軟件書的空白(本書為“基礎(chǔ)篇”，隨后將會(huì)編輯出版“高級篇”)。本書結(jié)合作者十多年的工作經(jīng)驗(yàn)，系統(tǒng)地介紹了fpga/cpld的基本設(shè)計(jì)方法，lattice主流fpga/cpld的結(jié)構(gòu)與特點(diǎn)，lattice工具軟件以及設(shè)計(jì)流程，lattice器件相關(guān)的常用調(diào)試手段和技巧，lattice提供的系統(tǒng)解決方案等?！　”緯涮坠獗P中收錄了isplever starter軟件以及書中所有實(shí)例的完整工程文件、設(shè)計(jì)源文件，并提供了部分lattice器件的技術(shù)手冊，便于讀者邊學(xué)邊練，提高實(shí)際應(yīng)用能力。　　本書可作為硬件工程師和邏輯工程師的實(shí)用工具書，也可以作為高等院校通信工程、電子工程、計(jì)算機(jī)、微電子與半導(dǎo)體等專業(yè)的教材和課外輔導(dǎo)書籍。

書籍目錄

第1章　fpga/cpld簡介　 　1.1　可編程邏輯設(shè)計(jì)技術(shù)簡介　 　　1.1.1　可編程邏輯器件發(fā)展簡史　 　　1.1.2　可編程邏輯器件的分類　 　1.2　fpga/cpld的基本結(jié)構(gòu)　 　　1.2.1　fpga的基本結(jié)構(gòu)　 　　1.2.2　cpld的基本結(jié)構(gòu)　 　　1.2.3　fpga和cpld的比較　 　1.3　fpga/cpld的設(shè)計(jì)流程　 　1.4　fpga/cpld的常用開發(fā)工具　 　1.5　下一代可編程邏輯設(shè)計(jì)技術(shù)展望　 　　1.5.1　下一代可編程邏輯器件硬件上的發(fā)展趨勢　 　　1.5.2　下一代eda軟件設(shè)計(jì)方法發(fā)展趨勢　 　1.6　小結(jié)　 　1.7　問題與思考　 第2章　lattice可編程邏輯器件的結(jié)構(gòu)和特點(diǎn)　 　2.1　cpld器件　 　　2.1.1　ispmach 4000 cpld的結(jié)構(gòu)和特點(diǎn)　 　　2.1.2　未來cpld的替代產(chǎn)品machxo　 　　2.1.3　machxo2系列器件　 　2.2　fpga器件　 　　2.2.1　非易失(non-volatile)xp/xp2系列fpga　 　　2.2.2　高性價(jià)比的ecp2m/ecp3系列fpga　 　　2.2.3　即將面世的ecp4系列fpga　 　2.3　可編程數(shù)模混合器件　 　　2.3.1　可編程電源管理芯片的結(jié)構(gòu)和特點(diǎn)　 　　2.3.2　可編程時(shí)鐘管理芯片的結(jié)構(gòu)和特點(diǎn)　 　2.4　小結(jié)　 　2.5　問題與思考　第3章　isplever fpga開發(fā)流程入門　 第4章　isplever fpga開發(fā)流程進(jìn)階　 第5章　lattice常用輔助設(shè)計(jì)工具　 第6章　lattice fpga/cpld的加載配置　 第7章　lattice ip開發(fā)工具　 第8章　第三方eda工具　 第9章　lattice系列fpga開發(fā)系統(tǒng)　

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