計(jì)算機(jī)系統(tǒng)組成與體系結(jié)構(gòu)

內(nèi)容概要

本書詳述了有關(guān)計(jì)算機(jī)及其子系統(tǒng)設(shè)計(jì)的基本概念及相關(guān)知識(shí)。全書由三大部分組成：第一部分是數(shù)字邏輯和有限狀態(tài)機(jī)，介紹了布爾代數(shù)基礎(chǔ)、數(shù)字部件、組合邏輯和順序邏輯、可編程邏輯器件。有限狀態(tài)機(jī)是全書的基礎(chǔ)。第二部分是計(jì)算機(jī)組成和系統(tǒng)結(jié)構(gòu)，內(nèi)容包括指令集系統(tǒng)結(jié)構(gòu)、計(jì)算機(jī)組成、寄存器傳輸語(yǔ)言、CPU設(shè)計(jì)、控制部件設(shè)計(jì)、算術(shù)運(yùn)算、存儲(chǔ)器結(jié)構(gòu)、I/O結(jié)構(gòu)。第三部分是高級(jí)專題，內(nèi)容包括RISC計(jì)算機(jī)和并行處理。   本書內(nèi)容適度、可讀性好、實(shí)用性強(qiáng)，適合作為計(jì)算機(jī)工程、計(jì)算機(jī)科學(xué)、電子工程、信息系統(tǒng)等專業(yè)的計(jì)算機(jī)體系結(jié)構(gòu)課程的教材。

書籍目錄

PARI 1 DIGITAL LOGIC AND FINITE STATE MACHINES  CHAPTER 1 DIGITAL LOGIC FUNDAMENTALS    1.1 Boolean Algebra     1.2 Basic Combinatorial Logic    1.3 More Complex Combibatorial Components    1.4 Combinatirial Circuit Designs    1.5 Basic Sequential Components    1.6 More Complex Sequential Components    1.7 REAL WORLD EXAMPLE:PROGRAMMABLE LOGIC DEVICES    1.8 Summary  CHAPTER 2 INTRODUCTION TO FINITE STATE MACHINES    2.1 State Diagrams and State Tables    2.2 Mealy and Moore Machines    2.3 Designing State Diagrams    2.4 From State Diagram to lmplementation    2.5 REAL WORLD EXAMPLE:PRACTICAL CONSIDERATIONS    2.6 SummaryPART 2 COMPUTER ORGANIZATION AND ARCHITECTURE  CHAPTER  3 INSTRRCTION SET ARCHITECTURES    3.1 Levels of Programming Languages     3.2 Assembly Language Instructions    3.3 Instruction Set Archigecture Design    3.4 A Relatively Simple Instruction Set Architecture    3.5 REAL WORLD EXAMPLE:THE 8085MICROPROCESSOR INSTRUCRION SET ARCHITECTURE    3.6 Summary   CHAPTER 4 INTRODUCTION TO COMPUTER ORGANEZATION    4.1 Basic Computer Organization     4.2 CPU Organization    4.3 Memory Subsystem Organization and Interfacing    4.4 I/O Subsystem Organization and Interfacing    4.5 A Relatively Simple Computer    4.6 REAL WORLD EXAMPLE:AN 8085-BASED COMPUTER    4.7 Summary  CHAPTER 5 REGISTER TRANSFER LANGUAGES    5.1 Micro-Operations and Register Transfer Language     5.2 Using RTL to Specify Digital Systems    5.3 More Complex Digital Systems and RTL    5.4 REAL WORLD EXAMPLE:VHDL-VHSIC HARDWARE DESCRIPTION LANGUAGE    5.5 Summary  CHAPTER 6 CPU DESIGN    6.1 Specifying     6.2 Design and Implementateon of a Very Simple CPU    6.3 Design and Implementation of a Relatively Simple CPU    6.4 Shortcomings of the Simple CPUs    6.5 REAL WORLD EXAMPLE:INTERNAL ARCHITECTURE OF THE 8085-INTEL MICROPROCESSOR    6.6 Summary  CHAPTER 7 MICROSEQUENCER CONTROL UNIT DESIGN    7.1 Basic microsequencer Design     7.2 Design and Implementation of a Very Simple Microsequencer    7.3 Design and Implementation of a Relatively Simple Microsequencer    7.4 Reducing the Number of Microinstructeons    7.5 Microprogrammed Control VS.Hardwired Control    7.6 REAL WORLD EXAMPLE:A(MOSTLY)MICROCODED CPU:THE PENTIUM PROCESSOR    7.7 Summary  CHAPTER 8 COMPUTER ARITHMETIC    8.1 Unsigned Notation     8.2 Signed Notation    8.3 Binary Coded Decimal    8.4 Specialized Arithmetic Hardware    8.5 Floating Poing Numbers    8.6 REAL WORLD EXAMPLE:THE IEEE754FLOATING POINT STANDARD    8.7 Summary  CHAPTER 9 MEMORY ORGANIZATION    9.1 Hierarchical Memory Systems     9.2 Cache Memory    9.3 Virtual Memory    9.4 Beyond the Basics of Cache and Virtual Memory    9.5 REAL WORLD EXAMPLE:MEMORY MANAGEMENT IN A PENTIUM/WINDOWS PERSONAL COMPUTER    9.6 Summary   CHAPTER 10 INPUT/PUTPUT ORGANIZATION    10.1 Asynchronous Data Transfers     10.2 Programmed I/O    10.3 Interrupts    10.4 Direct Memory Access    10.5 I/O Processors    10.6 Serial Communication    10.7 REAL WORLD EXAMPLE:SERIAL COMMUNICATION STANDARDS    10.8 Summary PART 3 ADVANCED TOPICS  CHAPTER 11 REDUCED INSTRUCTION SET COMPUTING    11.1 RISC Rationale     11.2 RISC Instruction    11.3 Instruction Pipelines and Register Windows    11.4 Instruction Pipeline Conflicts    11.5 RISC VS.CISC    11.6 REAL WORLD EXAMPLE:THE ITANIUM MICROPROCESSOR    11.7 Summary   CHAPTER 12 INTRODUCTION TO PARALLEL PROCESSING    12.1 Parallelism in Uniprocessor Systems     12.2 Organization of Multiprocessor Systems    12.3 Communication in Multistage Interconnection    12.4 Memory Organization in Multiprocessor Systems    12.5 Multiprocessor Operating Systems and Software    12.6 Parallel Algorithms    12.7 Alternative Parallel Architectures    12.8 Summary INDES

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