計算機體系結(jié)構(gòu)

內(nèi)容概要

　　《計算機體系結(jié)構(gòu)：量化研究方法（英文版·第5版）》堪稱計算機系統(tǒng)結(jié)構(gòu)學(xué)科的“圣經(jīng)”，是計算機設(shè)計領(lǐng)域?qū)W生和實踐者的必讀經(jīng)典。本書系統(tǒng)地介紹了計算機系統(tǒng)的設(shè)計基礎(chǔ)、存儲器層次結(jié)構(gòu)設(shè)計、指令級并行及其開發(fā)、數(shù)據(jù)級并行、GPU體系結(jié)構(gòu)、線程級并行和倉庫級計算機等?！　‖F(xiàn)今計算機界處于變革之中：移動客戶端和云計算正在成為驅(qū)動程序設(shè)計和硬件創(chuàng)新的主流范型。因此在這個最新版中，作者考慮到這個巨大的變化，重點關(guān)注了新的平臺（個人移動設(shè)備和倉庫級計算機）和新的體系結(jié)構(gòu)（多核和GPU），不僅介紹了移動計算和云計算等新內(nèi)容，還討論了成本、性能、功耗、可靠性等設(shè)計要素。每章都有兩個真實例子，一個來源于手機，另一個來源于數(shù)據(jù)中心，以反映計算機界正在發(fā)生的革命性變革。　　本書內(nèi)容豐富，既介紹了當(dāng)今計算機體系結(jié)構(gòu)的最新研究成果，也引述了許多計算機系統(tǒng)設(shè)計開發(fā)方面的實踐經(jīng)驗。另外，各章結(jié)尾還附有大量的習(xí)題和參考文獻(xiàn)。本書既可以作為高等院校計算機專業(yè)高年級本科生和研究生學(xué)習(xí)“計算機體系結(jié)構(gòu)”課程的教材或參考書，也可供與計算機相關(guān)的專業(yè)人士學(xué)習(xí)參考。

作者簡介

　　John L. Hennessy
斯坦福大學(xué)校長，IEEE和ACM會士，美國國家工程研究院院士及美國科學(xué)藝術(shù)研究院院士。Hennessy教授因為在RISC技術(shù)方面做出了突出貢獻(xiàn)而榮獲2001年的Eckert-Mauchly獎?wù)拢彩?001年Seymour
Cray計算機工程獎得主，并且和本書另外一位作者David A. Patterson分享了2000年John von
Neumann獎。
　　David A. Patterson
加州大學(xué)伯克利分校計算機科學(xué)系主任、教授，美國國家工程研究院院士，IEEE和ACM會士，曾因成功的啟發(fā)式教育方法被IEEE授予James
H. Mulligan，Jr.教育獎?wù)隆?/pre>


書籍目錄
ForewordPrefaceAcknowledgmentsChapter 1 Fundamentals of Quantitative Design and Analysis1.1 Introduction1.2 Classes of Computers1.3 Defining Computer Architecture1.4 Trends in Technology1.5 Trends in Power and Energy in Integrated Circuits1.6 Trends in Cost1.7 Dependability1.8 Measuring, Reporting, and Summarizing Performance1.9 Quantitative Principles of Computer Design1.10 Putting It All Together: Performance, Price, and Power1.11 Fallacies and Pitfalls1.12 Concluding Remarks1.13 Historical Perspectives and References Case Studies and Exercises by Diana FranklinChapter 2 Memory Hierarchy Design2.1 Introduction2.2 Ten Advanced Optimizations of Cache Performance2.3 Memory Technology and Optimizations2.4 Protection: Virtual Memory and Virtual Machines2.5 Crosscutting Issues: The Design of Memory Hierarchies2.6 Putting It All Together: Memory Hierachies in the ARM Cortex-AS and Intel Core i72.7 Fallacies and Pitfalls2.8 Concluding Remarks: Looking Ahead2.9 Historical Perspective and References Case Studies and Exercises by Norman P. Jouppi, Naveen Muralimanohar, and Sheng LiChapter 3 nstruction-Level Parallelism and Its Exploitation3.1 Instruction-Level Parallelism: Concepts and Challenges3.2 Basic Compiler Techniques for Exposing ILP3.3 Reducing Branch Costs with Advanced Branch Prediction3.4 Overcoming Data Hazards with Dynamic Scheduling3.5 Dynamic Scheduling: Examples and the Algorithm3.6 Hardware-Based Speculation3.7 Exploiting ILP Using Multiple Issue and Static Scheduling3.8 Exploiting ILP Using Dynamic Scheduling, Multiple Issue, and Speculation3.9 Advanced Techniques for Instruction Delivery and Speculation3.10 Studies of the Limitations oflLP3.11 Cross-Cutting Issues: ILP Approaches and the Memory System3.12 Multithreading: Exploiting Thread-Level Parallelism to Improve Uniprocessor Throughput3.13 Putting It All Together: The Intel Core i7 and ARM Cortex-AS3.14 Fallacies and Pitfalls3.15 Concluding Remarks: What's Ahead?3.16 Historical Perspective and References Case Studies and Exercises by Jason D. Bakos and Robert R ColwellChapter4 Data-Level Parallelism in Vector, SIMD, and GPU Architectures4.1 Introduction4.2 Vector Architecture4.3 SIMD Instruction Set Extensions for Multimedia4.4 Graphics Processing Units4.5 Detecting and Enhancing Loop-Level Parallelism4.6 Crosscutting Issues4.7 Putting It All Together: Mobile versus Server GPUS and Tesla versus Core i74.8 Fallacies and Pitfalls4.9 Concluding Remarks4.10 Historical Perspective and References Case Study and Exercises by Jason D. BakosChapter 5 Thread-Level Parallelism5.1 Introduction5.2 Centralized Shared-Memory Architectures5.3 Performance of Symmetric Shared-Memory Multiprocessors……Chapter6 Warehouse-Scale Computers to Exploit Request-Level and Data-Level ParallelismAppendix A Instruction Set PrinciplesAppendix B Review of Memory HierarchyAppendix C Pipelining: Basic and Intermediate Concepts


章節(jié)摘錄
版權(quán)頁：插圖：The pressure of both a fast clock cycle and power limitations encourages limited size for first-level caches. Similarly, use of lower levels of associativity can reduce both hit time and power, although such trade-offs are more complex than those involving size.The critical timing path in a cache hit is the three-step process of addressing the tag memory using the index portion of the address, comparing the read tag value to the address, and setting the multiplexor to choose the correct data item if the cache is set associative. Direct-mapped caches can overlap the tag check with the transmission of the data, effectively reducing hit time. Furthermore, lower levels of associativity will usually reduce power because fewer cache lines must be accessed.Although the total amount of on-chip cache has increased dramatically with new generations of microprocessors, due to the clock rate impact arising from a larger L1 cache, the size of the L1 caches has recently increased either slightly or not at all. In many recent processors, designers have opted for more associativity rather than larger caches. An additional consideration in choosing the associativity is the possibility of eliminating address aliases; we discuss this shortly.One approach to determining the impact on hit time and power consumption in advance of building a chip is to use CAD tools. CACTI is a program to estimate the access time and energy consumption of alternative cache structures on CMOS microprocessors within 10% of more detailed CAD tools. For a given minimum feature size, CACTI estimates the hit time of caches as cache size varies, associativity, number of read/write ports, and more complex parameters. Figure 2.3 shows the estimated impact on hit time as cache size and associativity are varied.



媒體關(guān)注與評論
“本書之所以成為永恒的經(jīng)典，是因為它的每一次再版都不僅僅是更新補充，而是一次全面的修訂，對這個激動人心且快速變化領(lǐng)域給出了最及時的信息和最獨到的解讀。對于我來說,即使已有二十多年的從業(yè)經(jīng)歷，再次閱讀本書仍自覺學(xué)無止境,感佩于兩位卓越大師的淵博學(xué)識和深厚功底?！?——Luiz Andre Barroso，Google公司


編輯推薦
《計算機體系結(jié)構(gòu):量化研究方法(英文版?第5版)》特色：更新相關(guān)內(nèi)容以覆蓋移動計算變革，并強調(diào)當(dāng)今體系結(jié)構(gòu)中最重要的兩個主題：存儲器層次結(jié)構(gòu)和各種并行技術(shù)。每章中的“Putting It All Together”小節(jié)關(guān)注了業(yè)界的各種最新技術(shù)，包括ARM Cortex-A8、Intel Core i7、NVIDIAGTX-280和GTX-480 GPU，以及一種Google倉庫級計算機。每章都設(shè)計了常規(guī)主題：能力、性能、成本、可依賴性、保護、編程模型和新趨勢。書中包括3個附錄，另外8個附錄可以在原出版社網(wǎng)站在線得到。每章最后都設(shè)置了由工業(yè)界和學(xué)術(shù)界專家提供的經(jīng)過更新的案例研究，以及與之配套的全新練習(xí)題。





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