復(fù)雜SoC設(shè)計(jì)

內(nèi)容概要

本書首次對以處理器為核心的SoC設(shè)計(jì)進(jìn)行了統(tǒng)一的硬件/軟件設(shè)計(jì)指導(dǎo)，是一本全面的、以實(shí)例為導(dǎo)向的指導(dǎo)書，能夠幫助讀者使用可配置的、可擴(kuò)展的處理器來創(chuàng)建設(shè)計(jì)項(xiàng)目?！　”緯肨ensilica公司的Xtensa結(jié)構(gòu)和TIE語言，系統(tǒng)地闡明了以處理器為核心進(jìn)行設(shè)計(jì)的問題、機(jī)遇和挑戰(zhàn)。Rowen介紹了一種全新的設(shè)計(jì)方法，然后介紹了其基本技術(shù)：處理器配置、擴(kuò)展、硬件/軟件協(xié)同生成、多處理器劃分/通信等。    本書內(nèi)容還包括： 　　●為什么可擴(kuò)展的處理器是必需的：當(dāng)前設(shè)計(jì)方法有什么缺點(diǎn)。 　　●將可擴(kuò)展的處理器結(jié)構(gòu)與傳統(tǒng)的處理器及硬連線邏輯電路相比較。 　　●延遲、吞吐率、并行功能的協(xié)調(diào)、硬件互連選擇、設(shè)計(jì)復(fù)雜度的管理等問題。 　　●針對嵌入式系統(tǒng)的多處理器SoC結(jié)構(gòu)。 　　●從軟件和硬件開發(fā)者角度觀察的任務(wù)設(shè)計(jì)。 　　●先進(jìn)的技術(shù)：實(shí)現(xiàn)復(fù)雜的狀態(tài)機(jī)、任務(wù)-任務(wù)之間的同步、功率優(yōu)化等。

作者簡介

　  Chris Rowen博士 Tensilica公司 (在高產(chǎn)量系統(tǒng)中，該公司在使用專用微處理器的自動生成方面居于領(lǐng)先地位) 的總裁、CEO和創(chuàng)始人。他在斯坦福大學(xué)參與了RISC結(jié)構(gòu)的最初研發(fā)工作，幫助創(chuàng)建了MIPS Computer Systems公司，并曾在Synopsys公司任Design Reuse Group (設(shè)計(jì)復(fù)用集

書籍目錄

1. The Case for a New SOC Design Methodology    1.1 The Age of Megagate SOCs    1.2 The Fundamental Trends of SOC Design    1.3 What’s Wrong with Today’s Approach to SOC Design?    1.4 Preview: An Improved Design Methodology for SOC Design    1.5 Further Reading2. SOC Design Today    2.1 Hardware System Structure    2.2 Software Structure    2.3 Current SOC DesignFlow    2.4 The Impact of Semiconductor Economics    2.5 Six Major Issues in SOC Design    2.6 Further Reading.3. A New Look at SOC Design    3.1 Accelerating Processors for Traditional Software Tasks    3.2 Example: Tensilica Xtensa Processors for EEMBC Benchmarks    3.3 System Design with Multiple Processors    3.4 New Essentials of SOC Design Methodoloy    3.5 Addressing the Six Problems    3.6 Further Reading4. System-Level Design of Complex SOCs     4.1 Complex SOC System Architecture Opportunities    4.2 Major Decisions in Processor-Centric SOC Organization    4.3 Communication Design = Software Mode + Hardware　Interconnect    4.4 Hardware Interconnect Mechanisms    4.5 Performance-Driven Communication Design    4.6 The SOC Design Flow    4.7 Non-Processor Building Blocks in Complex SOC    4.8 Implications of Processor-Centric SOC Architecture    4.9 Further Reading5. Configurable Processors: A Software View    5.1 Processor Hardware/Software Cogeneration    5.2 The Process of Instruction Definition and Application Tuning    5.3 The Basics of Instruction Extension    5.4 The Programmer’s Mode    5.5 Processor Performance Factors    5.6 Example: Tuning a Large Task    5.7 Memory-System Tuning    5.8 Long Instruction Words    5.9 Fully Automatic Instruction-Set Extension    5.10 Further Reading6. Configurable Processors: A Hardware View    6.1 Application Acceleration: A Common Problem    6.2 Introduction to Pipelines and Processors    6.3 Hardware Blocks to Processors    6.4 Moving from Hardwired Engines to Processors    6.5 Designing the Processor Interface    6.6 A Short Example: ATM Packet Segmentation and Reassembly    6.7 Novel Roles for Processors in Hardware Replacement    6.8 Processors, Hardware Implementation, and Verification Flow    6.9 Progress in Hardware Abstraction    6.10 Further Reading7. Advanced Topics in SOC Design    7.1 Pipelining for Processor Performance    7.2 Inside Processor Pipeline Stalls    7.3 Optimizing Processors to Match Hardware    7.4 Multiple Processor Debug and Trace    7.5 Issues in Memory Systems    7.6 Optimizing Power Dissipation in Extensible Processors    7.7 Essentials of TIE    7.8 Further Reading8. The Future of SOC Design: The Sea of Processors    8.2 Why Is Software Programmability So Central?    8.3 Looking into the Future of SOC    8.4 Processor Scaling Model    8.5 Future Applications of Complex SOCs    8.6 The Future of the Complex SOC Design Process    8.7 The Future of the Industry    8.8 The Disruptive-Technology View    8.9 The Long View    8.10 Further ReadingIndex

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