數(shù)字設(shè)計

內(nèi)容概要

　　第1章給出了本書中的一些基本定義和基礎(chǔ)規(guī)則，無論它們是否重要?！　〉?章介紹了二進制數(shù)制系統(tǒng)和編碼。第3章描述了數(shù)字電路的操作，重點描述了邏輯器件的外部電氣特性。第4章講解了組合邏輯的設(shè)計原理，包括開關(guān)代數(shù)與組合電路分析、綜合和最小化。第5章給出了基于硬件描述語言的設(shè)計的基本介紹，接下來提供了三種基本硬件描述語言ABEL、VHDL和 Verilog的學(xué)習(xí)指導(dǎo)。第6章首先討論了數(shù)字系統(tǒng)的文檔標(biāo)準(zhǔn)，這通常是開始真正的電路設(shè)計時最重要的部分。第7章講述的是時序邏輯設(shè)計原理，從介紹鎖存器和觸發(fā)器開始。第8章的內(nèi)容是介紹同步時序電路的設(shè)計實踐。第9 章介紹了存儲器件、CPLD和FPGA的有關(guān)知識?！　”緯拇蟛糠终鹿?jié)都包括了參考文獻、練習(xí)題和習(xí)題。

作者簡介

　　John F.Wakerly，于美國斯坦福大學(xué)獲得電子工程博士學(xué)位。他是思科公司廣域網(wǎng)業(yè)務(wù)部主管工程項目的副總裁，且擔(dān)任斯坦福大學(xué)的兼職教授。著有關(guān)于數(shù)字設(shè)計、微型計算機體系結(jié)構(gòu)、計算機可靠性等方面的50余部著作，并在網(wǎng)絡(luò)領(lǐng)域擁有13項專利。

書籍目錄

前言　1　引論　1.1　關(guān)于數(shù)字設(shè)計　　1.2　模擬與數(shù)字　1.3　數(shù)字器件　　1.4　數(shù)字設(shè)計中的電子方面　　1.5　數(shù)字設(shè)計中的軟件方面　1.6　集成電路　1.7　可編程邏輯器件　1.8　專用集成電路　1.9　印刷電路板　1.10　數(shù)字設(shè)計層次　1.11　以游戲之名　1.12　進一步探討　　練習(xí)題2　數(shù)字系統(tǒng)和編碼　2.1　進位計數(shù)制　2.2　八進制數(shù)和十六進制數(shù)　2.3　常見的進位計數(shù)制轉(zhuǎn)換　2.4　非十進制數(shù)的加法和減法　2.5　負數(shù)的表示法　2.6　二進制補碼的加法和減法　2.7　反碼的加法和減法　2.8　二進制乘法　2.9　二進制除法　2.10　十進制數(shù)的二進制編碼　2.11　格雷碼　2.12　字符編碼　2.13　行為、條件和狀態(tài)的編碼　2.14　n立方和距離　2.15　檢錯碼和糾錯碼　2.16　用于串行數(shù)據(jù)傳輸和存儲的編碼　參考文獻　練習(xí)題　習(xí)題　3　數(shù)字電路　　3.1　邏輯信號和門　3.2　邏輯系列　　3.3　CMOS邏輯　3.4　CMOS電路的電氣特性　3.5　CMOS的靜態(tài)電氣特性　3.6　CMOS的動態(tài)電氣特性　3.7　其他CMOS輸入輸出結(jié)構(gòu)　3.8　CMOS邏輯系列　3.9　低壓CMOS邏輯和接口　3.10　雙極邏輯　參考文獻　練習(xí)題　習(xí)題4　組合邏輯的設(shè)計原理　4.1　開關(guān)代數(shù)　4.2　組合電路分析　4.3　組合電路綜合　4.4　時序冒險　參考文獻　練習(xí)題　習(xí)題5　硬件描述語言　　5.1　基于硬件描述語言的數(shù)字設(shè)計　5.2　硬件描述語言ABEL　5.3　硬件描述語言VHDL　5.4　硬件描述語言Verilog　參考文獻　練習(xí)題　習(xí)題6　組合邏輯的設(shè)計實踐　6.1　文檔標(biāo)準(zhǔn)　6.2　電路時序　6.3　組合型可編程邏輯陣列PLD　6.4　譯碼器　6.5　編碼器　6.6　三態(tài)器件　6.7　多路復(fù)用器　6.8　異或門和奇偶校驗電路　6.9　比較器　6.10　加法器、減法器和算術(shù)邏輯部件　6.11　組合乘法器　參考文獻　練習(xí)題　習(xí)題7　時序邏輯設(shè)計原理　7.1　雙穩(wěn)態(tài)元件　7.2　鎖存器和觸發(fā)器　7.3　時序同步狀態(tài)機分析　7.4　時序同步狀態(tài)機設(shè)計　7.5　用狀態(tài)圖設(shè)計狀態(tài)機　7.6　用轉(zhuǎn)換表綜合狀態(tài)機　7.7　其他狀態(tài)機設(shè)計實例　7.8　分解狀態(tài)機　　7.9　反饋時序電路分析　7.10　反饋時序電路設(shè)計　7.11　ABEL時序電路設(shè)計特性　7.12　用VHDL實現(xiàn)時序電路設(shè)計　7.13　用Verilog實現(xiàn)時序電路設(shè)計　參考文獻　練習(xí)題　習(xí)題8　時序邏輯設(shè)計實踐　8.1　時序電路的文檔標(biāo)準(zhǔn)　8.2　鎖存器和觸發(fā)器　8.3　時序PLD　8.4　計數(shù)器　8.5　移位寄存器　8.6　迭代電路與時序電路　8.7　同步設(shè)計方法　8.8　同步設(shè)計中的障礙　8.9　同步器失敗和亞穩(wěn)態(tài)　參考文獻　練習(xí)題　習(xí)題9　存儲器、CPID和FPGA　9.1　只讀存儲器　9.2　讀/寫存儲器　9.3　靜態(tài)RAM　9.4　動態(tài)RAM　9.5　復(fù)雜可編程邏輯器件　9.6　現(xiàn)場可編程門陣列　參考文獻　練習(xí)題　習(xí)題索引

章節(jié)摘錄

　　Many people helped make this book possible. Most of them helped with the first three editions and are acknowledged there. Preparation of the fourth edition has been a very lonely task, but it was made easier by my friends Prem Jain and Mike V　　lpi at Cisco Systems. They and the company made it possible for me to cut back my commitment at Cisco to less than half time for the ten months that it took to prepare this revised edition.　　For the ideas on the "principles" side of this book, I still owe great thanks to my teacher, research advisor, and friend Ed McCluskey. On the "practices" side, Dave Raaum, one of the leading members of my "Digital Designers Hall of Fame" reviewed the new Verilog material and provided many suggestions.　　Since the third edition was published, I have received many helpful comments from readers. In addition to suggesting or otherwise motivating many improvements, readers have spotted dozens of typographical and technical errors whose fixes are incorporated in this fourth edition.　　My sponsoring editor at Prentice Hall, Tom Robbins, deserves thanks for shepherding this project over the past years. Hes the third or fourth editor who has changed jobs after （almost） completing one of my book projects, leading me to wonder whether working with me inevitably leads to burnout or success or both （and if so, then in which order?）. Special thanks go to Toms boss, Marcia Horton, who took over after his departure. If youre reading this, then she did a terrific job of pulling this one out of the fire ！　　Copy editor and proofreader Jennie Kaufman did a marvelous j　　b of ensuring consistency and catching typos, including several that had been overlooked by me and everyone else since the second or third edition. Production editor Scott Disanno also deserves credit for providing a very smooth interface with the production side of the house and for inspiring me with his very quick response times during the final "crunch" stage of the project.

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