時(shí)鐘發(fā)生器在片上系統(tǒng)處理器中的應(yīng)用

內(nèi)容概要

　　《時(shí)鐘發(fā)生器在片上系統(tǒng)處理器中的應(yīng)用》針對在SOC芯片上使用的全集成頻率合成器的設(shè)計(jì)，從電路和系統(tǒng)的角度對鎖相環(huán)的原理和設(shè)計(jì)進(jìn)行了分析。特別是在電路層次上，討論了深亞微米CMOS數(shù)字工藝中的低電壓模擬電路的設(shè)計(jì)，有比較大的參考意義。在對鎖相環(huán)基本工作原理分析的基礎(chǔ)之上，《時(shí)鐘發(fā)生器在片上系統(tǒng)處理器中的應(yīng)用》分析了具體的時(shí)鐘產(chǎn)生方案和電路設(shè)計(jì)問題，并進(jìn)一步討論了鎖相環(huán)的應(yīng)用?！稌r(shí)鐘發(fā)生器在片上系統(tǒng)處理器中的應(yīng)用》還包括了PLL可測試性設(shè)計(jì)的內(nèi)容。最后還從宏觀角度討論了SOC時(shí)鐘域的設(shè)計(jì)。書中包含的大量實(shí)際問題分析應(yīng)該有助于讀者更好地理解時(shí)鐘產(chǎn)生器設(shè)計(jì)中的核心問題。

書籍目錄

ABOUT THE AUTHORPREFACEFOREWORD1.INTRODUCTION1.1 WHAT ARE SYSTEM-ON-A-CHIP PROCESSORS?1.2 ORGANIZATION2.PHASE-LOCKED LOOP FUNDAMENTALS2.1 Introduction2.2 PLL Basics2.3 Continuoas-time Linear Analysis of PLLs2.4 Discrete-time Linear Analysis of PLLs2.5 Nonlinear Locking Behaviour of PLLs2.6 Summary3.LOW-VOLTAGE ANALOG CMOS DESIGN3.1 Introduction3.2 MOS Transistors3.3 Low-Voltage Current Mirrors3.4 Low- Voltage Charge Pumps3.5 Low- Voltage Oscillator Design3.6 Voltage and Current References3.7 Summary4.JITTER ANALYSIS IN PHASE-LOCKED LOOPS4.1 Introduction4.2 Jitter Basics4.3 Jitter in Voltage Controlled Oscillators4.4 Jitter Performance of Closed-Loop PLL System4.5 Coupling Noise Effects on Jitter4.6 Summary5.LOW-JITTER PLL ARCHITECTURES5.1 Introduction5.2 Differential PLL Architecture.5.3 Supply Voltage Regulated PLL Architectures5.4 Adaptive PLL Architectures5.5 Resistorless Loop Filter PLLs5.6 Delay-Locked Loop Frequency Multipliers5.7 Summary6.DIGITAL PLL DESIGN6.1 Introduction6.2 Basic Topology6.3 Z-domain Analysis6.4 Circuit Implementation Issues6.5 Alternate Digital PLL for Clock Generation6.6 Summary7.DSP CLOCK GENERATOR ARCHITECTURES7.1 Introduction7.2 Sampling Clock Requirements for Data Converters7.3 Jitter in Frequency Dividers7.4 Fractional-N PLLs as Clock Generators7.5 Oversampled PLL Topologies7.6 Direct Digital Synthesis with Analog Interpolation7.7 Summary8.DESIGN FOR TESTABILITY IN PLLS8.1 Introduction8.2 Verification of SoC PLLs8.3 Jitter Measurement Techniques8.4 Design for Testability and Self-Test in PLLs8.5 Summary9.CLOCK PARTITIONING AND SKEW CONTROL9.1 Introduction9.2 Clock Distribution Networks in SoCs9.3 Performance Limitations in Clock Networks9.4 Active Skew Management Strategies9.5 Multi-phase Clock Generator9.6 Low-Power Clock Distribution Strategies9.7 Multi-clock Domain Interfacing9.8 SummaryINDEX

編輯推薦

　　Clock Generators for SOC Processors　　This book examines the issue of design of fully-integrated frequency synthesizers suitable for system-on-a-chip（soc）processors．　　This book takes a more global design perspective in jointly examining the design space at the circuit level as well as at the architectural level．The coverage of the book is comprehensive and includes summary chapters on circuit theory as well as feedback control theory relevant to the operation of phase locked loops（PLLs）．　　On the circuit level，the discussion includes low-voltage analog design in deep submicron digital CMOS processes，effects of supply noise，substrate noise，as well device noise．On the architectural level，the discussion includes PLLanalysis using continuous-time as well as discrete-time models，linear and nonlirear effects of PLL performance，and detailed analysis of locking behavior．

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