VLSI的統(tǒng)計(jì)分析和優(yōu)化

內(nèi)容概要

該書介紹了集成電路的統(tǒng)計(jì)CAD工具的相關(guān)知識。主要面向CAD工具開發(fā)人員、集成電路工藝技術(shù)人員，以及相關(guān)學(xué)科的學(xué)生和研究人員。書中介紹了統(tǒng)計(jì)時(shí)序和功耗分析技術(shù)中的最新研究成果，并結(jié)合參數(shù)化的產(chǎn)量作為設(shè)計(jì)過程中的主要目標(biāo)函數(shù)。該書強(qiáng)調(diào)算法、過程變量的建模方法，以及統(tǒng)計(jì)方法。既可作為剛涉足CAD工具開發(fā)領(lǐng)域的人員的入門書籍，也可作為該領(lǐng)域工程師的參考手冊。

書籍目錄

Preface1 Introduction　1.1 Sources of Variations　　1.1.1 Process Variations　　1.1.2 Environmental Variations　　1.1.3 Modeling Variations　　1.1.4 Other Sources of Variations　1.2 Components of Variation　　1.2.1 Inter-die Variations　　1.2.2 Intra-die Variations　1.3 Impact on Performance2 Statistical Models and Techniques.　2.1 Monte Carlo Techniques　　2.1.1 Sampling Probability Distributions　2.2 Process Variation Modeling　　2.2.1 Pelgrom's Model　　2.2.2 Principal Components Based Modeling　　2.2.3 Quad-Tree Based Modeling　　2.2.4 Specialized Modeling Techniques　2.3 Performance Modeling　　2.3.1 Response Surface Methodology　　2.3.2 Non-Normal Performance Modeling　　2.3.3 Delay Modeling　　2.3.4 Interconnect Delay Models　　2.3.5 Reduced-Order Modeling Techniques3 Statistical Timing Analysis　3.1 Introduction　3.2 Block-Based Timing Analysis　　3.2.1 Discretized Delay PDFs　　3.2.2 Reconvergent Fanouts　　3.2.3 Canonical Delay PDFs　　3.2.4 Multiple Input Switching　3.3 Path-Based Timing Analysis　3.4 Parameter-Space Techniques　　3.4.1 Parallelepiped Method　　3.4.2 Ellipsoid Method　　3.4.3 Case-File Based Models for Statistical Timing　3.5 Bayesian Networks4 Statistical Power Analysis　4.1 Overview　4.2 Leakage Models　4.3 High-Level Statistical Analysis　4.4 Gate-Level Statistical Analysis　　4.4.1 Dynamic Power　　4.4.2 Leakage Power　　4.4.3 Temperature and Power Supply Variations5 Yield Analysis　5.1 High-Level Yield Estimation　　5.1.1 Leakage Analysis　　5.1.2 Frequency Binning　　5.1.3 Yield Computation　5.2 Gate-Level Yield Estimation　　5.2.1 Timing Analysis　　5.2.2 Leakage Power Analysis　　5.2.3 Yield Estimation　5.3 Supply Voltage Sensitivity6 Statistical Optimization Techniques　6.1 Optimization of Process Parameters　　6.1.1 Timing Constraint　　6.1.2 Objective Function　　6.1.3 Yield Allocation　6.2 Gate Sizing　　6.2.1 Nonlinear Programming　　6.2.2 Lagrangian Relaxation　　6.2.3 Utility Theory　　6.2.4 Robust Optimization　　6.2.5 Sensitivity-Based Optimization　6.3 Buffer Insertion　　6.3.1 Deterministic Approach　　6.3.2 Statistical Approach　6.4 Threshold Voltage Assignment　　6.4.1 Sensitivity-Based Optimization　　6.4.2 Dynamic ProgrammingReferencesIndex

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