傳感器和通信中的CMOS級(jí)聯(lián)式Sigma

內(nèi)容概要

　　CMOS級(jí)聯(lián)式Sigma-Delta調(diào)節(jié)器是近年來(lái)研究的熱點(diǎn)，作為一種較新的結(jié)構(gòu)形式，國(guó)內(nèi)外都比較重視。尤其是對(duì)于ADC的研究，作為數(shù)?；旌螩MOS電路的研究典型，在國(guó)內(nèi)非常熱?！秱鞲衅骱屯ㄐ胖械腃MOS級(jí)聯(lián)式Sigma-Delta調(diào)制器（影印版）》對(duì)sigma-delta調(diào)制器作了全面的分析，深入探討了其在傳感器接口和無(wú)線通信中的應(yīng)用。對(duì)誤差分析、級(jí)連結(jié)構(gòu)、電路、模型，以及實(shí)際設(shè)計(jì)重點(diǎn)考慮的內(nèi)容，都進(jìn)行了全面的闡述?！秱鞲衅骱屯ㄐ胖械腃MOS級(jí)聯(lián)式Sigma-Delta調(diào)制器（影印版）》與其他同類書不同之處在于其完整、深入地對(duì)開關(guān)電容電路的誤差進(jìn)行了詳細(xì)分析。　　《傳感器和通信中的CMOS級(jí)聯(lián)式Sigma-Delta調(diào)制器（影印版）》內(nèi)容全面、由淺入深、適用面廣、適合相關(guān)專業(yè)的高級(jí)科技工作者和研究生參考，對(duì)高年級(jí)本科生也具有參考價(jià)值。

書籍目錄

PrefaceList of AbbreviationsCHAPTER 1 ∑△ ADCs: Principles, Architectures, and State of the Art1.1. Analog-to-Digital Conversion: Fundamentals1.1.1. Sampling1.1.2. Quantization1.2. Oversampling ∑△ ADCs: Fundamentals1.2.1. Oversampling1.2.2. Noise-shaping1.2.3. Basic architecture of oversampling ZA ADCs1.2.4. Performance metrics1.2.5. Ideal performance1.3. Single-Loop ∑△ Architectures1.3.1. 1st-order ∑△ modulator1.3.2. 2nd-order ∑△ modulator1.3.3. High-order ∑△ modulatorsStability concernsOptimized NTFsHigh-order topologiesNon-linear stabilization techniques1.4. Cascade ∑△ Architectures1.5. Multi-Bit ∑△ ArchitecturesInfluence of DAC errors1.5.1. Element trimming and analog calibration1.5.2. Digital correction1.5.3. Dynamic element matching1.5.4. Dual-quantizationLeslie-Singh architectureSingle-loop ∑△MsCascade ∑△Ms1.6. Parallel ∑△ Architectures1.6.1. Frequency division multiplexing1.6.2. Time division multiplexing1.6.3. Code division multiplexing1.7. State of the Art in ∑△ ADCs1.8. SummaryCHAPTER 2 Non-ldeal Performance of ∑△ Modulators2.1. Integrator LeakageLeaky integrator2.1.1. Single-loop ∑△ modulators1st-order loop2nd-order loopLth-order loops2.1.2. Cascade ∑△ modulators2.2. Capacitor Mismatch2.2.1. Single-loop ∑△ modulators2nd-order loopLth-order loops2.2.2. Cascade ∑△ modulators2.3. Integrator Settling Error2.3.1. Model for the transient response of SC integratorsSC integrator modelTransient during integrationTransient during samplingIntegration-sampling process2.3.2, Validation of the proposed modelComparison with experimental resultsComparison with traditional models2.3.3. Effect of the amplifier finite gain-bandwidth productSingle-loop ∑△ modulatorsCascade ∑△ modulators2.3.4. Effect of the amplifier finite slew rate2.3.5. Effect of the switch finite on-resistanceEffect on an ideal integratorEffect on the amplifier GBEffect on the amplifier SR2.4. Circuit Noise2.4.1. Noise in track-and-holdsTrack component……CHAPTER 3 A Wideband ZA Modulator in 3．3-V 0．35-um CMOSCHAPTER 4 A∑△Modulator in 2．5-V 0．25-um CMOS for ADSUADSL+CHAPTER 5 A∑△Modulator with Programmable Signal Gain for Automotive Sensor Inte~acesAPPENDIX A An Expandible Family of Cascade∑△ModulatorsAPPENDIX B Power Estimator for Cascade∑△ModulatorsREFERENCESIndex

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