系統(tǒng)集成

內(nèi)容概要

　　本書(shū)介紹了涉及集成電路組件的集成和設(shè)計(jì)的較寬范圍的內(nèi)容，提供給讀者用簡(jiǎn)單公式估計(jì)晶體管幾何尺寸和推演電路行為的方法。這本獨(dú)特的書(shū)廣泛覆蓋場(chǎng)效應(yīng)管的設(shè)計(jì)、MOS管的建模和數(shù)字CMOS集成電路設(shè)基礎(chǔ)以及MOS存儲(chǔ)器結(jié)構(gòu)和設(shè)計(jì)。本書(shū)突出了在片上系統(tǒng)設(shè)計(jì)和集成方面知識(shí)增加的需求，第一次在單本中覆蓋半導(dǎo)體物理學(xué)、數(shù)字VLSI設(shè)計(jì)和模擬集成電路，介紹了集成電路半導(dǎo)體組件的基本行為和基于MOS與BiCMOS工藝的數(shù)字和模擬集成電路的設(shè)計(jì)。

書(shū)籍目錄

PrefaceAcknowledgmentsPhysical Constants and Conversion FactorsSymbols1 Semiconductor Physics1.1 Band Theory of Solids1.2 Doped Semiconductor1.3 Semiconductor in Equilibrium1.3.1 Fermi-Dirac Distribution Function1.3.2 Carrier Concentration at Equilibrium1.3.3 Density Product at Equilibrium1.3.4 Relationship between Energy, Voltage, and Electrical Field1.4 Charge Transport1.4.1 Drift Velocity1.4.2 Drift Current1.4.3 Diffusion Current1.4.4 Continuity Equation1.5 Non-Equilibrium ConditionsProblemsReferencesFurther Reading2 pn-Junction2.1 Inhomogeneously Doped n-type Semiconductor2.2 pn-Junction at Equilibrium2.3 Biased pn-Junction2.3.1 Density Product under Non-Equilibrium Conditions2.3.2 Current-Voltage Relationship2.3.3 Deviation from the Current-Voltage Relationship2.3.4 Voltage Reference Point2.4 Capacitance Characteristic2.4.1 Depletion Capacitance2.4.2 Diffusion Capacitance2.5 Switching Characteristic2.6 Junction Breakdown2.7 Modeling the pn-Junction2.7.1 Diode Model for CAD Applications2.7.2 Diode Model for Static Calculations2.7.3 Diode Model for Small-Signal CalculationsProblemsReferences3 Bipolar Transistor3.1 Bipolar Technologies3.2 Transistor Operation3.2.1 Current-Voltage Relationship3.2.2 Transistor under Reverse Biased Condition3.2.3 Voltage Saturation3.2.4 Temperature Behavior3.2.5 Breakdown Behavior3.3 Second-Order Effects3.3.1 High Current Effects3.3.2 Base-Width Modulation3.3.3 Current Crowding3.4 Alternative Transistor Structures3.5 Modeling the Bipolar Transistor3.5.1 Transistor Model for CAD Applications3.5.2 Transistor Model for Static Calculations3.5.3 Transistor Model for Small-Signal Calculations3.5.4 Transit Time DeterminationProblemsReferencesFurther Reading4 MOS Transistor4.1 CMOS Technology4.2 The MOS Structure4.2.1 Characteristic of the MOS Structure4.2.2 Capacitance Behavior of the MOS Structure4.2.3 Flat-Band Voltage4.3 Equations of the MOS Structure　4.3.1 Charge Equations of the MOS Structure4.3.2 Surface Voltage at Strong Inversion4.3.3 Threshold Voltage and Body Effect4.4 MOS Transistor4.4.1 Current-Voltage Characteristic at Strong Inversion4.4.2 Improved Transistor Equation4.4.3 Current-Voltage Characteristic at Weak Inversion4.4.4 Temperature Behavior4.5 Second-Order Effects4.5.1 Mobility Degradation4.5.2 Channel Length Modulation4.5.3 Short Channel Effects4.5.4 Hot Electrons4.5.5 Gate-Induced Drain Leakage4.5.6 Breakdown Behavior4.5.7 Latch-up Effect4.6 Power Devices4.7 Modeling of the MOS Transistor4.7.1 Transistor Model for CAD Applications4.7.2 Transistor Model for Static and Dynamic Calculations4.7.3 Transistor Model for Small-Signal CalculationsProblemsAppendix A Current-Voltage Equation of the MOS Transistor　under Weak Inversion ConditionReferencesFurther Reading5 Basic Digital CMOS Circuits5.1 Geometric Design Rules5.2 Electrical Design Rules5.3 MOS Inverter5.3.1 Depletion Load Inverter5.3.2 Enhancement Load Inverter5.3.3 PMOS Load Inverter5.3.4 CMOS Inverter5.3.5 Ratioed Design Issues5.4 Switching Performance of the Inverters5.5 Buffer Stages5.5.1 Super Buffer5.5.2 Bootstrap Buffer5.6 Input/Output Stage5.6.1 Input Stage5.6.2 Output Stage5.6.3 ESD ProtectionProblemsReferences6 Combinational and Sequential CMOS Circuits6.1 Static Combinational Circuits6.1.1 Complementary Circuits6.1.2 PMOS Load Circuits6.1.3 Pass-Transistor Circuits6.2 Clocked Combinational Circuits6.2.1 Clocked CMOS Circuits (C2MOS)6.2.2 Domino Circuits6.2.3 NORA Circuits6.2.4 Differential Cascaded Voltage Switch Circuits (DCVS)6.2.5 Switching Performance of Ratioless Logic6.3 High Speed Circuits6.4 Logic Arrays6.4.1 Decoder6.4.2 Programmable Logic Array6.5 Sequential Circuits6.5.1 Flip-flop6.5.2 Two-Phase Clocked Register6.5.3 One-Phase Clocked Register6.5.4 Clock Distribution and GenerationProblemsReferencesFurther Reading7 MOS Memories7.1 Read Only Memory7.2 Electrically Programmable and Optically Erasable Memory7.2.1 EPROM Memory Architecture7.2.2 Current Sense Amplifier7.3 Electrically Erasable and Programmable Read Only Memories7.3.1 EEPROM Memory Cells7.3.2 Flash Memory Architectures7.3.3 On-Chip Voltage Generators7.4 Static Memories7.4.1 Static Memory Cells7.4.2 SRAM Memory Architecture7.4.3 Address Transition Detection7.5 Dynamic Memories7.5.1 One-Transistor Cell7.5.2 Basic DRAM Memory Circuits7.5.3 DRAM Architecture7.5.4 Radiation Effects in MemoriesProblemsReferencesFurther Reading8 Basic Analog CMOS Circuits8.1 Current Mirror8.1.1 Improved Current Sources8.2 Source Follower8.3 Basic Amplifier Performance8.3.1 Miller Effect8.3.2 Differential Stage with Symmetrical Output8.3.3 Differential Input Stage with Single-Ended OutputProblemsAppendix A Transfer FunctionsFurther Reading9 CMOS Amplifiers9.1 Miller Amplifier9.2 Folded Cascode Amplifier9.3 Folded Cascode Amplifier with Improved Driving CapabilityProblemsReferences10 BICMOS10.1 Current Steering Techniques10.1.1 CML Circuits10.1.2 ECL Circuits10.2 BICMOS Buffer and Gates10.3 Band-Gap Reference Circuits10.4 Analog Applications10.4.1 Offset Voltage of Bipolar and MOS Transistors10.4.2 Comparison of Small-Signal PerformanceProblemsReferencesIndex

編輯推薦

　　本書(shū)涉及集成電路組件的集成和設(shè)計(jì)的較寬范圍的內(nèi)容，提供給讀者用簡(jiǎn)單公式估計(jì)晶體管幾何尺寸和推演電路行為的方法。本書(shū)廣泛覆蓋場(chǎng)效應(yīng)管的設(shè)計(jì)、MOS管的建模和數(shù)字CMOs集成電路設(shè)計(jì)基礎(chǔ)以及MOS存儲(chǔ)器結(jié)構(gòu)和設(shè)計(jì)。本書(shū)突出了片上系統(tǒng)設(shè)計(jì)和集成方面知識(shí)的需求，在單本書(shū)中覆蓋半導(dǎo)體物理學(xué)、數(shù)字VLSI設(shè)計(jì)和模擬集成電路，介紹了集成電路半導(dǎo)體組件的基本行為和基于CMOS與BiCMOS工藝的數(shù)字和模擬集成電路的設(shè)計(jì)。

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