CMOS鎖相環(huán)

內(nèi)容概要

本書(shū)是一本關(guān)于小型sigma-delta頻率綜合器方面的優(yōu)秀著作。作者分別從系統(tǒng)級(jí)和電路級(jí)對(duì)頻率綜合器的設(shè)計(jì)進(jìn)行了闡述。主要?jiǎng)?chuàng)新點(diǎn)在低功耗高速分頻器和減少芯片面積的環(huán)路濾波器的電容設(shè)計(jì)上。該書(shū)涉及PLL的基礎(chǔ)問(wèn)題，內(nèi)容全面翔實(shí)，由淺入深，對(duì)PLL的關(guān)鍵問(wèn)題提出了解決方案。

書(shū)籍目錄

PrefaceList of Acronyms and Symbols1 Introduction　1.1 MOTIVATION　1.2 SUMMARY OF BOOK　1.3 BOOK ORGANIZATION　REFERENCES2 Frequency Synthesizer for Wireless Applications　2.1 DEFINITION AND CHARACTERISTICS　2.2 PHASE NOISE AND TIMING JITTER　　2.2.1 Phase noise and spurious tone　　2.2.2 Timing jitter　2.3 IMPLEMENTATION OF FREQUENCY SYNTHESIZER　　2.3.1 Direct analog frequency synthesizer　　2.3.2 Direct digital frequency synthesizer　　2.3.3 PLL-based frequency synthesizer　　2.3.4 DLL-based frequency synthesizer ~...　　2.3.5 Hybrid frequency synthesizer :.　　2.3.6 Summary and comparison of synthesizers　2.4 FREQUENCY SYNTHESIZER FOR WIRELESS TRANSCEIVERS　2.5 OTHER APPLICATIONS OF PLL AND FREQUENCY SYNTHESIZER　REFERENCES3 PLL Frequency Synthesizer　3.1 PLL FREQUENCY SYNTHESIZER BASICS　　3.1.1 Basic building blocks of charge-pump PLL　　3.1.2 Continuous-time linear phase analysis　　3.1.3 Locking time　　3.1.4 Tracking and acquisition　3.2 FAST-LOCKING TECHNIQUES　　3.2.1 Bandwidth gear-shifting　　3.2.2 VCO pre-tuning　3.3 DISCRETE-TIME ANALYSIS AND NONLINEAR MODELING　　3.3.1 z-domain transfer function and stability analysis　　3.3.2 Nonlinear dynamic behavior modeling　3.4 DESIGN EXAMPLE: 2.4GHZ INTEGER-N PLL FOR BLUETOOTH　REFERENCES4 ∑△ FractionaI-N PLL Synthesizer　4.1 ∑△ FRACTIONAL-N FREQUENCY SYNTHESIZER　　4.1.1 ∑△ quantization noise to phase noise mapping　　4.1.2 ∑△ quantization noise to timing jitter mapping　4.2 A COMPARATIVE STUDY OF DIGITAL ∑△ MODULATORS　　4.2.1 Design considerations　　4.2.2 Four types of digital ∑△ modulators　　4.2.3 Summary of comparative study　4.3 OTHER APPLICATIONS OF EA-PLL　　4.3.1 Direct digital modulation　　4.3.2 Frequency-to-digital conversion　4.4 MODELING AND SIMULATION OF ∑△-PLL　4.5 DESIGN EXAMPLE: 900MHz ∑△-PLL FOR GSM　REFERENCES5 Enhanced Phase Switching Prescaler　5.1 PRESCALERARCHITECTURE　　5.1.1 Conventional prescaler　　5.1.2 Phase switching prescaler　　5.1.3 Injection-locked prescaler　　5.1.4 Summary and comparison of prescalers　5.2 ENHANCED PHASE-SWITCHING PRESCALER　5.3 CIRCUIT DESIGN AND SIMULATION RESULTS　　5.3.1 Eight 45~-spaced phases generation　　5.3.2 8-to-1 multiplexer　　5.3.3 Switching control circuit　　5.3.4 Asynchronous frequency divider　5.4 DELAY BUDGET IN THE SWITCHING CONTROL LOOP　5.5 SPURS DUE TO NONIDEAL 45 PHASE SPACING　REFERENCES6 Loop Filter With Capacitance Multiplier　6.1 LOOP FILTER ARCHITECTURE　　6.1.1 Passive loop filter　　6.1.2 Dual-path loop filter　　6.1.3 Sample-reset loop filter　　6.1.4 Other loop filter architectures　　6.1.5 Summary and comparison of loop filters　6.2 LOOP FILTER AND CHARGE-PUMP NOISE MAPPING　6.3 LOOP FILTER WITH CAPACITANCE MULTIPLIER　　6.3.1 Third-order passive loop filter　　6.3.2 Capacitance multiplier　　6.3.3 Simulation of loop filter with capacitance multiplier　　6.3.4 Noise consideration　REFERENCES7 Other Building Blocks of PLL　7.1 VCO　　7.1.1 LC-VCO　　7.1.2 Varactor　　7.1.3 Inductor　　7.1.4 VCOphase noise　　7.1.5 Layout　7.2 PHASE-FREQUENCY DETECTOR　　7.3 CHARGE-PUMP　　7.3.1 Reference spur　　7.3.2 Charge pump architectures　7.4 PROGRAMMABLE DIVIDER　7.5 DIGITAL MODULATOR　7.6 CHIP LAYOUT　REFERENCES8 Prototype Measurement Results　8.1 PRESCALER MEASUREMENT　8.2 LOOP FILTER MEASUREMENT　8.3 PLL MEASUREMENT　REFERENCES9 ConclusionsAppendixIndex

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