超高頻多速開關(guān)電容電路設(shè)計(jì)

內(nèi)容概要

　　《超高頻多速開關(guān)電容電路設(shè)計(jì)（影印版）》是一本專業(yè)性很強(qiáng)的書，《超高頻多速開關(guān)電容電路設(shè)計(jì)（影印版）》以具體實(shí)例為依托，詳細(xì)闡述了作者所設(shè)計(jì)的一款性能優(yōu)越、用途廣泛的高頻開關(guān)電容電路，并對(duì)該電路設(shè)計(jì)中所涉及到的模擬CMOS集成電路設(shè)計(jì)的很多重要問題進(jìn)行講解。其實(shí)這些問題并不僅僅出現(xiàn)于《超高頻多速開關(guān)電容電路設(shè)計(jì)（影印版）》所介紹的這種電路類型，而是在模擬集成電路設(shè)計(jì)中經(jīng)常會(huì)遇到的一些問題，所以該書的參考價(jià)值可以擴(kuò)展到更大的領(lǐng)域。更難能可貴的是作者所設(shè)計(jì)的這款電路的優(yōu)越性能得到了實(shí)際芯片測(cè)試的驗(yàn)證，亦即增加了《超高頻多速開關(guān)電容電路設(shè)計(jì)（影印版）》的權(quán)威性。

書籍目錄

PrefaceAcknowledgmentList of AbbreviationsList of FiguresList of Tables1 INTRODUCTION1. High-Frequency Integrated Analog Filtering2. Multirate Switched-Capacitor Circuit Techniques3. Sampled-Data Interpolation Techniques4. Research Goals and Design Challenges2 IMPROVED MULTIRATE POLYPHASE-BASED INTERPOLATION STRUCTURES1. Introduction2. Conventional and Improved Analog Interpolation3. Polyphase Structures for Optimum-class Improved Analog Interpolation4. Multirate ADB Polyphase Structures4.1 Canonic and Non-Canonic ADB Realizations4.2 SC Circuit Architectures5. Low-Sensitivity Multirate IIR Structures5.1 Mixed Cascade/Parallel Form5.2 Extra-Ripple IIR Form6. Summary3 PRACTICAL MULTIRATE SC CIRCUIT DESIGN CONSIDERATIONS1. Introduction2. Power Consumption Analysis3. Capacitor-Ratio Sensitivity Analysis3.1 FIR Structure3.2 IIR Structure4. Finite Gain & Bandwidth Effects5. Input-Referred Offset Effects6. Phase Timing-Mismatch Effects6.1 Periodic Fixed Timing-Skew Effect6.2 Random Timing-Jitter Effects7. Noise Analysis8. Summary4 GAIN- AND OFFSET- COMPENSATION FOR MULTIRATE SC CIRCUITS1. Introduction2. Autozeroing and Correlated-Double Sampling Techniques3. AZ and CDS SC Delay Blocks with Mismatch-Free Property3.1 SC Delay Block Architectures3.2 Gain and Offset Errors - Expressions and Simulation Verification3.3 Multi-Unit Delay Implementations4. AZ and CDS SC Accumulators4.1 SC Accumulator Architectures4.2 Gain and Offset Errors - Expressions and Simulation Verification5. Design Examples6. Speed and Power Considerations7. Summary5 DESIGN OF A 108 MHz MULTISTAGE SC VIDEO INTERPOLATING FILTER1. Introduction2. Optimum Architecture Design2.1 Multistage Polyphase Structure with Half-Band Filtering..2.2 Spread-Reduction Scheme2.3 Coefficient-Sharing Techniques3. Circuit Design3.1 lst-Stage3.2 2nd- and 3rd-Stage3.3 Digital Clock Phase Generation4. Circuit Layout5. Simulation Results5.1 BehavioraI Simulations5.2 Circuit-Level Simulations6. Summary6 DESIGN OF A 320 MHZ FREQUENCY-TRANSLATED SC BANDPASS INTERPOLATING FILTER1. Introduction2. Prototype System-Level Design2.1 Multi-notch FIR Transfer Function2.2 Time-Interleaved Serial ADB Polyphase Structure withA utozeroing3. Prototype Circuit-Level Design3.1 Autozeroing ADB and Accumulator3.2 High-Speed Multiplexer3.3 Overall SC Circuit Architecture3.4 Telescopic opamp with Wide-Swing Biasing3.5 nMOS Switches 1363.6 Noise Calculation3.7 I/0 Circuitry3.8 Low Timing-Skew Clock Generation4. Layout Considerations4.1 Device and Path Matching4.2 Substrate and Supply Noise Decoupling4.3 Shielding4.4 Floor Plan5. Simulation Results5.1 Opamp Simulations5.2 Filter Behavioral Simulations5.3 Filter Transistor-Level and Post-Layout Simulations6. Summary7 EXPERIMENTAL RESULTS1. Introduction2. PCB Design2.1 Floor Plan2.2 Power Supplies and Decoupling2.3 Biasing Currents2.4 Input and Output Network3. Measurement Setup and Results3.1 Frequency Response3.2 Time-Domain Signal Waveforms3.3 One-Tone Signal Spectrum3.4 Two-Tone Intermodulation Distortion3.5 THD and IM3 vs. Input Signal Level3.6 Noise Performance3.7 CMRR and PSRR4. Summary8 CONCLUSIONSAPPENDIX 1 TIMING-MISMATCH ERRORS WITH NONUNIFORMLY HOLDING EFFECTS1. Spectrum Expressions for IU-ON（SH） and IN-CON（SH）1.1 IU-ON（SH）1.2 IN-CON（SH）2. Closed Form SINAD Expression for IU-ON（SH） and IN-CON（SH）2.1 IU-ON（SH）2.2 IN-CON（SH）3. Closed Form SFDR Expression for IN-CON（SH） systems4. Spectrum Correlation of IN-OU（IS） and IU-ON（SH）APPENDIX 2 NOISE ANALYSIS FOR SC ADB DELAY LINE AND POLYPHASE SUBFILTERS1. Output Noise of ADB Delay Line2. Output Noise of Polyphase Subfilters2.1 Using TSI Input Coefficient SC Branches2.2 Using OFR Input Coefficient SC BranchesAPPENDIX 3 GAIN， PHASE AND OFFSET ERRORS FOR GOC MF SC DELAY CIRCUIT I AND J1. GOC MF SC Delay Circuit I2. GOC MF SC Delay Circuit J

編輯推薦

　　《超高頻多速開關(guān)電容電路設(shè)計(jì)（影印版）》所論述的高頻開關(guān)電容電路屬于相關(guān)領(lǐng)域的研究熱點(diǎn)，是集成電路設(shè)計(jì)中不可回避的前沿問題。此外，書中提出的設(shè)計(jì)方法具有很強(qiáng)的啟發(fā)性和指導(dǎo)性。相關(guān)的著作很少見，相信該書具有很高的權(quán)威性。

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