寬帶高動態(tài)范圍DAC

內(nèi)容概要

　　寬帶高動態(tài)范圍DAC是現(xiàn)代信息系統(tǒng)的基本構(gòu)件。目前的電流舵DAC具有在較寬的頻率范圍內(nèi)取得高動態(tài)性能的潛力。然而，它們在更高頻率時的性能被非線性限制了。寬帶高動態(tài)范圍DAC是解決這一缺陷的有效方法?！秾拵Ц邉討B(tài)范圍DAC（影印版）》的亮點在于提出了詳細的方案，可以解決由失配和時鐘串?dāng)_引起的時序誤差，實現(xiàn)了12位、采樣率500M、0.18微米工藝的高性能DAC。

書籍目錄

PrefaceGlossaryAbbreviations1 Digital to Analog conversion concepts1.1 Functional aspects1.1.1 Definition of the D/A function1.1.2 Functional specifications1.2 Algorithmic aspects1.3 Signal processing aspects1.3.1 Waveforms and Line coding1.3.2 Signal Modulation concepts1.4 Circuit aspects1.4.1 Architecture terminology1.4.2 Resistive voltage division architectures1.4.3 Capacitive voltage and charge division architectures1.4.4 Current division based architectures1.5 Conclusions2 Framework for Analysis and Synthesis of DACs2.1 Overview2.2 Framework description2.2.1 Analysis2.2.2 Synthesis3 Current Steering DACs3.1 Basic circuit3.1.1 Partitioning and segmentation3.1.2 Current switching network and current sources3.1.3 Clock-data synchronization circuit3.1.4 Auxiliary circuits3.2 Implementations and technology impact4 Dynamic limitations of Current Steering DACs4.1 State of the art in dynamic linearity4.2 Dynamic limitations of current steering DACs4.2.1 Matching and relative amplitude precision4.2.2 Matching and relative timing precision4.3 Conclusions5 Current Steering DAC circuit error analysis5.1 Amplitude domain errors5.1.1 Relative amplitude inaccuracies5.1.2 Output resistance modulation5.2 Time domain errors5.2.1 Nonlinear settling and output impedance modulation5.2.2 Asymmetrical switching5.2.3 Modulation of switching behavior5.2.4 Charge feedthrough and injection5.2.5 Relative timing inaccuracies5.2.6 Power supply bounce and substrate noise5.2.7 Clock (timing) jitter5.3 Conclusions6 High-level modeling of Current Steering OACs6.1 System modeling6.1.1 System layers6.1.2 System excitations and responses6.1.3 System parameters6.1.4 Subsystem interaction6.1.5 System modulation6.2 Error properties and classification6.2.1 Error properties6.2.2 Error classification6.3 Functional error generation mechanisms6.3.1 Definitions6.3.2 Algorithmic modeling6.3.3 Functional modeling6.3.4 Examples……7 Functional modeling of timing errors8 Functional analysis of local timing errors9 Circuit analysis of local timing errors10 Synthesis concepts for CS DACs11 Design of a 12 bit 500 Msample/s DACReferencesA Output spectrum for timing errorsB Literature data

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